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Readout architectures for uncooled IR detector arrays
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Microelectronics Research Center, Ericsson Components AB, Stockholm, Sweden.
2000 (English)In: Sensors and Actuators A-Physical, ISSN 0924-4247, Vol. 84, no 3, 220-229 p.Article in journal (Refereed) Published
Abstract [en]

The main idea of this paper is to compare the readout architectures for uncooled microbolometer focal plane detector arrays with respect to the detector and readout circuit noise. The comparison is done keeping the total power consumption of all architectures constant. Three CMOS readout architectures with different degree of parallelism are described in this paper: pixelwise, columnwise and serial. The noise model of the readout circuit is given. Also, the optimization for the lowest NETD (noise equivalent temperature difference) and estimation of the self-heating effect is presented.

Place, publisher, year, edition, pages
2000. Vol. 84, no 3, 220-229 p.
National Category
Natural Sciences
URN: urn:nbn:se:liu:diva-47597DOI: 10.1016/S0924-4247(00)00313-7ISI: 000088801600005OAI: diva2:268493
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2013-12-18
In thesis
1. Signal readout and sampling in CMOS
Open this publication in new window or tab >>Signal readout and sampling in CMOS
2002 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

Advances in CMOS technology have resulted in high-performance and low-cost consumer electronics. One of the main driving forces in this progress is technology scaling. The development of integrated circuits is continuously moving to a system-on-chip realization. where the digital signal processing is integrated with analog and mixed-signal circuits. Designing a system-on-chip, architecture choice is important. Another issue is the high-performance analog-to-digital converter, which is often a bottleneck in the system-on-chip design.

An overview of the analog-to-digital conversion performance roadmap and possible applications is given in this licentiate thesis. A high-speed track-and-hold circuit is analyzed as a critical block in the analog-to-digital converter. The main sampling circuit nonidealities and limiting factors are formulated. Several solutions to improve the track-and-hold circuit performance are proposed. To verify the proposed ideas, test chips in 0.35-μm CMOS technology are designed and fabricated. The basic measurement methods are discussed to characterize the high-speed track and-hold circuit performance.

As an application of the analog-to-digital conversion, different receiver architectures are described and compared. The homodyne and the direct analog-to-digital conversion receiver architectures are found to be the most suitable ones for system-on-chip implementation. A new receiver architecture, which utilizes direct sampling at RF, is proposed. An improved high-speed sampling circuit is used in this architecture together with time-interleaved analog-to-digital conversion. The GSM-1800 specification is chosen as target.

Different readout architectures for uncooled IR detection are also described in this thesis. First, an introduction to the infrared detection and readout principles is presented. Next, the readout architectures are compared, considering different degrees of parallelism. The design parameters are optirnized to have the lowest noise equivalent temperature difference (NETD) and the power consumption is chosen to be equal in all readout architectures. The pixelwise architecture is found to have the lowest NETD and the most reasonable design parameters when a realistic noise model is considered.

To summarize the main contributions of this thesis, they are as follows: comparison of readout architectures for uncooled IR detector arrays; a MOS switch linearization method for high-speed sampling is proposed; a sampling error minimization method by using a differential clock is described; a radio architecture with an RF sampling receiver is proposed.

Place, publisher, year, edition, pages
Linköping: Linköping studies in science and technology, 2002. 26 p.
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 967
National Category
Engineering and Technology
urn:nbn:se:liu:diva-34862 (URN)23739 (Local ID)91-737-965-0 (ISBN)23739 (Archive number)23739 (OAI)
2002-09-02, Sal Algoritmen, Linköpings universitet, Linköping, 10:15 (Swedish)
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2013-12-18

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