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Pulsewidth control loop in high-speed CMOS clock buffers
SwitchCore, S-223 63 Lund, Sweden.
2000 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 35, no 2, 134-141 p.Article in journal (Refereed) Published
Abstract [en]

In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital. Signal quality degradation is influenced by temperature and process deviation. In this paper, we propose a pulsewidth control loop to get required pulsewidth. To investigate the loop stability, a linearized small signal analysis model is used. Results of SPICE simulation show that the pulsewidth can be well controlled if the loop parameters are properly chosen. The pulsewidth can be easily adjusted to a desired value by sizing the ratio of transistor sizes in the current mirror of charge pump.

Place, publisher, year, edition, pages
2000. Vol. 35, no 2, 134-141 p.
National Category
Natural Sciences
Identifiers
URN: urn:nbn:se:liu:diva-47718DOI: 10.1109/4.823439OAI: oai:DiVA.org:liu-47718DiVA: diva2:268614
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-13

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CiteExportLink to record
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