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Preemptive system-on-chip test scheduling
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2004 (English)In: IEICE transactions on information and systems, ISSN 0916-8532, Vol. E87D, no 3, 620-629 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we propose a preemptive test scheduling technique (a test can be interrupted and later resumed) for core-based systems with the objective to minimize the test application time. We make use of reconfigurable core test wrappers in order to increase the flexibility in the scheduling process. The advantage with such a wrapper is that it is not limited to a single TAM (test access mechanism) bandwidth (wrapper chain configuration) at each core. We model the scheduling problem as a Bin-packing problem, and we discuss the transformation: number of TAM wires (wrapper-chains) versus test time in combination with preemption, as well as the possibilities and the limitations to achieve an optimal solution in respect to test application time. We have implemented the proposed preemptive test scheduling algorithm, and we have through experiments demonstrated its efficiency.

Place, publisher, year, edition, pages
2004. Vol. E87D, no 3, 620-629 p.
Keyword [en]
test scheduling, test access mechanism design, preemptive scheduling, system-on-chip testing
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-48403OAI: diva2:269299
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2011-01-12

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Larsson, Erik
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The Institute of TechnologyESLAB - Embedded Systems Laboratory
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