Impact of CMOS technology scaling on the atmospheric neutron soft error rate
2000 (English)In: IEEE Transactions on Nuclear Science, ISSN 0018-9499, Vol. 47, no 6, 2586-2594 p.Article in journal (Refereed) Published
We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size L-G A different method, based on the MBGR model, predicts even faster decrease of SER per bit than linear If the increasing number of bits is taken into account, then the SER per chip is not expected to increase faster than linearly with decreasing L-G.
Place, publisher, year, edition, pages
2000. Vol. 47, no 6, 2586-2594 p.
circuit reliability, scaling, single event upset, soft error rate, technology characterization
IdentifiersURN: urn:nbn:se:liu:diva-49373OAI: oai:DiVA.org:liu-49373DiVA: diva2:270269