A global passive sampling technique for high-speed switched-capacitor time-interleaved ADCs
2000 (English)In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, Vol. 47, no 9, 821-831 p.Article in journal (Refereed) Published
In this paper, we present a passive sampling technique for time-interleaved switched capacitor analog-to-digital converters (ADCs), The purpose of the proposed sampling technique is to reduce the effect of delay skews between the sample and hold (S/H) circuits in the parallel channels, which limits the performance at high signal frequencies, If designed properly, the circuit can reduce the delay-skew related distortion by 10-20 dB compared to an architecture without a global input S/H circuit. Since no op amp needs to work at the full speed of the ADC, the circuit is suitable for high-speed and consumes less power than an architecture with an active input S/H circuit.
Place, publisher, year, edition, pages
2000. Vol. 47, no 9, 821-831 p.
parallel converter, switched-capacitor circuits, time-interleaved analog-to-digital converter, timing error
IdentifiersURN: urn:nbn:se:liu:diva-49589OAI: oai:DiVA.org:liu-49589DiVA: diva2:270485