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A global passive sampling technique for high-speed switched-capacitor time-interleaved ADCs
Linkoping Univ, Dept Elect Engn, S-58183 Linkoping, Sweden GlobeSpan Inc, Red Bank, NJ 07701 USA.
2000 (English)In: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print), ISSN 1057-7130, Vol. 47, no 9, 821-831 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we present a passive sampling technique for time-interleaved switched capacitor analog-to-digital converters (ADCs), The purpose of the proposed sampling technique is to reduce the effect of delay skews between the sample and hold (S/H) circuits in the parallel channels, which limits the performance at high signal frequencies, If designed properly, the circuit can reduce the delay-skew related distortion by 10-20 dB compared to an architecture without a global input S/H circuit. Since no op amp needs to work at the full speed of the ADC, the circuit is suitable for high-speed and consumes less power than an architecture with an active input S/H circuit.

Place, publisher, year, edition, pages
2000. Vol. 47, no 9, 821-831 p.
Keyword [en]
parallel converter, switched-capacitor circuits, time-interleaved analog-to-digital converter, timing error
National Category
Natural Sciences
Identifiers
URN: urn:nbn:se:liu:diva-49589OAI: oai:DiVA.org:liu-49589DiVA: diva2:270485
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2011-01-14

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IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print)
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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
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  • nn-NB
  • sv-SE
  • Other locale
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Output format
  • html
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