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Investigation on maximal throughput of a CMOS repeater chain
Linkoping Univ, Dept Phys, Div Elect Devices, SE-58183 Linkoping, Sweden.
2000 (English)In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 47, no 4, 602-606 p.Article in journal (Refereed) Published
Abstract [en]

This paper investigates the performance of a simple repeater chain interconnection for high-speed on-chip data transfer. The data in the repeater chain is distributed over a number of identical inverters, which are optimized with respect to size and position along the chain. It is shown how the distributed interconnection compares, in terms of throughput and power consumption, with a lumped driver consisting of several cascaded inverters with a stage ratio larger than one. The performance of the repeater chain has been demonstrated by design and measurement of a 0.8-mu m twin-well double-metal single-poly CMOS chip, in which a 4-mm repeater chain had a maximal data rate of 1.7 Gb/s at V-dd = 5 V.

Place, publisher, year, edition, pages
2000. Vol. 47, no 4, 602-606 p.
Keyword [en]
CMOS, high throughput, interconnection, repeaters
National Category
Natural Sciences
Identifiers
URN: urn:nbn:se:liu:diva-49753OAI: oai:DiVA.org:liu-49753DiVA: diva2:270649
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-12

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