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Test time minimization for hybrid BIST of core-based systems
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Linköping University, The Institute of Technology. Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
Department of Computer Engineering, Tallinn University of Technology, Estonia.
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2006 (English)In: Journal of Computer Science and Technology, ISSN 1000-9000, E-ISSN 1860-4749, Vol. 21, no 6, 907-912 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions. © Springer Science + Business Media, Inc. 2006.

Place, publisher, year, edition, pages
2006. Vol. 21, no 6, 907-912 p.
Keyword [en]
Hybrid BIST, Self-test, SoC
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-50096DOI: 10.1007/s11390-006-0907-xOAI: oai:DiVA.org:liu-50096DiVA: diva2:270992
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2017-12-12

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Jervan, GertEles, Petru IonPeng, Zebo

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