Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding
2010 (English)In: Journal of Signal Processing Systems for Signal, Image, and Video Technology, ISSN 1939-8018, Vol. 60, no 1, 15-29 p.Article in journal (Refereed) Published
This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today’s consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used indifferent standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm2 area in 65nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.
Place, publisher, year, edition, pages
2010. Vol. 60, no 1, 15-29 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-25599DOI: 10.1007/s11265-009-0394-8ISI: 000276722700002OAI: oai:DiVA.org:liu-25599DiVA: diva2:271855
The original publication is available at www.springerlink.com:
Rizwan Asghar, Di Wu, Johan Eilert and Dake Liu, Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding, 2010, Journal of Signal Processing Systems for Signal, Image, and Video Technology, (60), 1, 15-29.
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