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An Asic Perspective on FPGA Optimizations
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.ORCID iD: 0000-0002-0111-2384
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2009 (English)In: 19th International Conference on Field Programmable Logic and Applications (FPL), 2009, 218-223 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect the performance and area of an ASIC port. We find that most techniques that are used to optimize a design for an FPGA will not have a negative impact on the area in an ASIC. The intended audience for this paper are engineers charged with creating designs or IP cores that are optimized for both FPGAs and ASICs.

Place, publisher, year, edition, pages
2009. 218-223 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-50674DOI: 10.1109/FPL.2009.5272311ISI: 000277506300033ISBN: 978-1-4244-3892-1 (print)ISBN: 978-1-4244-3892-1 (print)OAI: oai:DiVA.org:liu-50674DiVA: diva2:271881
Conference
FPL 09: 19th International Conference on Field Programmable Logic and Applications; Prague; Czech Republic
Available from: 2009-10-13 Created: 2009-10-13 Last updated: 2015-02-18

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Ehliar, AndreasLiu, Dake

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