On implementation of fast, bit-serial loops
1996 (English)In: Proc. IEEE 39th Midwest Symp. Circuits and Systems, MWSCAS'96, 1996, I-190-I-193 p.Conference paper (Refereed)
In this paper we show that it is not sufficient to specify the latency of the processing elements without considering the throughput to arrive at a maximally fast implementation of a recursive algorithm. This result is due to the observation that the latency for serial multiplication actually is dependent on the throughput. We demonstrate how higher throughput is obtained for a first-order recursive filter by increasing the latency of the processing elements. Three models for the latency are examined from corresponding implementations of the filter. For one of the models, canonic signed-digit coding of the coefficient is used which results in a significant increase of the throughput of a serial/parallel multiplier.
Place, publisher, year, edition, pages
1996. I-190-I-193 p.
CMOS logic circuits, digital arithmetic, logic design, multiplying circuits, recursive filters
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50887DOI: 10.1109/MWSCAS.1996.594083ISBN: 0-7803-3636-4OAI: oai:DiVA.org:liu-50887DiVA: diva2:272299