Implementation of a bit-serial FFT processor with a hierarchical control structure
1995 (English)In: Proc. 1995 European Conf. on Circuit Theory and Design, ECCTD'95, 1995, I-423-I-426 p.Conference paper (Refereed)
A 128-point FFT/IFFT processor has been designed and implemented in a standard CMOS process using the TSPC logic style. The processor uses a high performance bit-serial SIC architecture and calculates an FFT in 58 ms. A structured technique to derive a hierarchical control structure from the pseudo-code for the FFT has been used, resulting in a control unit implemented as a set of co-operating bit-serial control processors. The computational requirements are met using only one butterfly-PE and two RAMs.
Place, publisher, year, edition, pages
1995. I-423-I-426 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50888OAI: oai:DiVA.org:liu-50888DiVA: diva2:272301