High-speed multiplication in bit-serial digital filters
1996 (English)In: Proc. IEEE Nordic Signal Processing Symp., NORSIG'96, 1996, 179-182 p.Conference paper (Refereed)
Canonic signed-digit code representation of multiplier coefficients is often used in digital filters to reduce the required amount of hardware resources. Another approach taken in this paper is to use canonic signed-digit coded coefficients to increase the throughput of the multiplier. We show how the suggested approach applies to serial/parallel multipliers with fixed coefficients. A max¬imally fast implementation of a digital filter is further used as an example to demonstrate the use of the multi¬pliers in recursive digital filters. The resulting bit-serial filters yield a throughput comparable to bit-parallel implemen¬tations, while using only a fractional amount of hardware resources. The filters can be used directly in high-speed applications or in low-power applications after supply voltage scaling.
Place, publisher, year, edition, pages
1996. 179-182 p.
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50892OAI: oai:DiVA.org:liu-50892DiVA: diva2:272304