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Arithmetic transformations for fast bit-serial VLSI implementations of recursive algorithms
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
1996 (English)In: Proc. IEEE Nordic Signal Processing Symp., NORSIG'96, 1996, 391-394 p.Conference paper, Published paper (Refereed)
Abstract [en]

A method to increase the throughput of static recursive algorithms is presented. The signal-flow graph is transformed by first minimizing the number of summation points in the computational loops. A second transformation to rewrite the fixed coefficient multiplications as a sum of weighted signals is then followed by a reordering of the summations. It is how a sum of products can be implemented in this way. Sharing of sub-expressions are also discussed. A bit-serial implementation of a third order bireciprocal lattice WDF is used to illustrate the transformations and sharing of sub-expressions.

Place, publisher, year, edition, pages
1996. 391-394 p.
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Other Electrical Engineering, Electronic Engineering, Information Engineering
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URN: urn:nbn:se:liu:diva-50896OAI: oai:DiVA.org:liu-50896DiVA: diva2:272305
Available from: 2009-10-06 Created: 2009-10-06 Last updated: 2009-10-15

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Palmkvist, KentVesterbacka, MarkWanhammar, Lars

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