Arithmetic transformations for fast bit-serial VLSI implementations of recursive algorithms
1996 (English)In: Proc. IEEE Nordic Signal Processing Symp., NORSIG'96, 1996, 391-394 p.Conference paper (Refereed)
A method to increase the throughput of static recursive algorithms is presented. The signal-flow graph is transformed by first minimizing the number of summation points in the computational loops. A second transformation to rewrite the fixed coefficient multiplications as a sum of weighted signals is then followed by a reordering of the summations. It is how a sum of products can be implemented in this way. Sharing of sub-expressions are also discussed. A bit-serial implementation of a third order bireciprocal lattice WDF is used to illustrate the transformations and sharing of sub-expressions.
Place, publisher, year, edition, pages
1996. 391-394 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50896OAI: oai:DiVA.org:liu-50896DiVA: diva2:272305