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A robust differential logic style with NMOS logic nets
n/a.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
1997 (English)In: Proc. IEE Int. Workshop on Signal Processing, IWSSIP'97, 1997, 61-64 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper a new dynamic differential logic style is presented. A non-precharged single phase clocking scheme is used. The logic is suitable for high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS and merged with the latches. The logic style is also robust for clock slope and yield a data noise margin equal to Vdd/2.

Place, publisher, year, edition, pages
1997. 61-64 p.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-50897OAI: oai:DiVA.org:liu-50897DiVA: diva2:272306
Available from: 2009-10-15 Created: 2009-10-15 Last updated: 2009-10-17

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Vesterbacka, MarkWanhammar, Lars

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