Design and implementation of a complex multiplier using distributed arithmetic
1997 (English)In: Proc. IEEE Workshop on Signal Processing Systems, SIPS'97, 1997, 222-231 p.Conference paper (Refereed)
We propose an efficient scheme for implementing a complex multiplier based on distributed arithmetic. A modified bit-serial shift-accumulator for distributed arithmetic is also proposed for computing a*b+c, where a, b and c are complex numbers. The shift-accumulator is highly regular and modular and consists of only three types of bit-slices, each of which consists of only three types of blocks, multiplexers, exclusive OR gates, and latches. The implementation is done using a robust differential single-phase clocked logic style suitable for high-speed and low power operation. The resulting implementation of the complex multiplier has a maximum clock frequency of 250 MHz, consumes 70 mW, and occupies a chip area of 0.5 mm2 in a double-metal 0.8 μm process. The coefficient word length and the data word length are 12 bits and 16 bits, respectively
Place, publisher, year, edition, pages
1997. 222-231 p.
digital arithmetic, flip-flops, logic design, logic gates, multiplying circuits
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50899DOI: 10.1109/SIPS.1997.626125ISBN: 0-7803-3806-5OAI: oai:DiVA.org:liu-50899DiVA: diva2:272308