Implementation of bit-serial adders using robust differential logic
1997 (English)In: Proc. NORCHIP'97, 1997, 366-373 p.Conference paper (Refereed)
In this paper two bit-serial carry save adders are implemented using a recently proposed differential logic style. The clocking scheme uses a single clock phase with non-precharged stages of logic that may be merged with the latches or the flip-flops. A novel flip-flop structure is used in one of the adders, which significantly lowers the number of clocked transistors. The logic style used in the adder realizations suits high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS. The logic style is also robust for clock slope and yields a data noise margin equal to Vdd/2. The adders reached a maximal clock frequency of 300 MHz in a 0.8 mm process with a 3.0 V power supply voltage.
Place, publisher, year, edition, pages
1997. 366-373 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50900OAI: oai:DiVA.org:liu-50900DiVA: diva2:272309