A non-overlapping two-phase clock generator with adjustable duty cycle
2003 (English)In: Electronic Proc. Nat. Symp. on Microwave Technique and High Speed Electronics, GHz'03, 2003Conference paper (Other academic)
In this paper, a new robust non-overlapping two-phase clock generator with adjustable duty cycle is proposed. The generator is based on a differential negative edge trigged D flip-flop and has small area and power consumption. The maximal clock rate and delay are also improved reaching a clock frequency of 1.0 GHz in a standard 0.35 µm CMOS process. The new clock generator is inherently glitch and spike free and robust against slow clock transitions, that reduces the design effort significantly.
Place, publisher, year, edition, pages
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50903OAI: oai:DiVA.org:liu-50903DiVA: diva2:272312