An FFT processor based on the SIC architecture with asynchronous PE
1996 (English)In: Proc. IEEE 1996 Midwest Symp. on Circuits and Systems, MWSCAS'96, 1996, III-1313-III-1316 p.Conference paper (Refereed)
A SIC architecture with asynchronous bit-serial PEs is presented and applied to the Sande-Tukey's FFT. The resulting architecture can easily be modified for higher throughput and/or lower power consumption. Using this architecture a high-performance chip for use in an OFDM transmission system has been designed.
Place, publisher, year, edition, pages
1996. III-1313-III-1316 p.
application specific integrated circuits, fading, fast Fourier transforms, frequency division multiplexing, intersymbol interference, mobile radio
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50910DOI: 10.1109/MWSCAS.1996.593171ISBN: 0-7803-3636-4OAI: oai:DiVA.org:liu-50910DiVA: diva2:272315