A robust differential scan flip-flop
1999 (English)In: Proc. 1999 IEEE Int. Symp. on Circuits and Systems, ISCAS'99, 1999, I-334-I-337 p.Conference paper (Refereed)
A flip-flop is proposed that is robust against smooth clock edges. This robustness simplifies the design of the clock net in large integrated circuits and lowers the power consumed in the clock driver compared to flip-flops needing sharper clock edges. The proposed flip-flop is realized using 20 MOSFETs and uses a single phase clock. It includes a multiplexer circuit at the input that is useful in a scan test. The flip-flop is semi-static in the sense that the master latch is static while the slave latch is dynamic. This allows the clock to be in the low state for an indefinitely long period, while the period of the high state is limited due to charge leakage. Therefore another circuit is also proposed that limits the pulse width of the clock. The use of this circuit enables design of a scan chain that can be clocked with an arbitrarily low frequency.
Place, publisher, year, edition, pages
1999. I-334-I-337 p.
CMOS logic circuits, flip-flops, high-speed integrated circuits, integrated circuit testing, logic testing
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50912DOI: 10.1109/ISCAS.1999.777871ISBN: 0-7803-5471-0OAI: oai:DiVA.org:liu-50912DiVA: diva2:272317