Reduction of Clock Noise in Mixed-Signal Circuits
2002 (English)In: Proc. National Conf. on Radio Science, RVK'02, 2002, Vol. 1, 197-201 p.Conference paper (Other academic)
A major concern in mixed-signal circuits is the noise injected by the digital circuits into sensitive analog circuits. Of particular interest in this work is the problem with large capacitive coupling between the digital clock network and the substrate shared with the analog circuits. It is in general more easy to reduce low frequency noise compared with high frequency noise. Therefore, we have developed a strategy where we reduce the high frequency content of the clock by using smooth clock edges, and a special digital flip-flop circuit. This strategy will be evaluated in a test chip where we can control the rise and fall time of the clock edges of a high-performance digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.
Place, publisher, year, edition, pages
2002. Vol. 1, 197-201 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-50926OAI: oai:DiVA.org:liu-50926DiVA: diva2:272330