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Digit-serial implementation of LDI/LDD allpass filters
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Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2002 (English)In: Proc. 2002 IEEE Int. Symp. on Circuits and Systems, ISCAS'02, 2002, II-684-II-687 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we study digit-serial implementation of the general-order lossless discrete integrator/differentiator (LDI/LDD) allpass filter structure. In low-power filter implementation, digit-serial computation has been shown to be advantageous compared to bit-serial and parallel arithmetics. The digit-serial processing elements are obtained using unfolding techniques. The implementation is compared to a corresponding wave digital (WD) implementation. It is shown in an example that a WD realization requires about 60% and 30% more D flip-flops for pipelining and shimming delays, respectively, than the corresponding LDI/LDD implementation. We also study the sample period of the second-order LDI/LDD allpass filter using different digit sizes and conclude that when the filter is scheduled over a number of sample periods we achieve the shortest sample period.

Place, publisher, year, edition, pages
2002. II-684-II-687 p.
Keyword [en]
all-pass filters, differentiating circuits, digital filters, integrating circuits, low-power electronics, pipeline processing
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-50935ISBN: 0-7803-7448-7 (print)OAI: oai:DiVA.org:liu-50935DiVA: diva2:272341
Available from: 2009-10-15 Created: 2009-10-15 Last updated: 2009-10-17

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Vesterbacka, Mark

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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf