Low-complexity reconfigurable complex constant multiplication for FFTs
2009 (English)In: IEEE International Symposium on Circuits and Systems, Piscataway: IEEE , 2009, 1137-1140 p.Conference paper (Refereed)
In this work we consider structures for simultaneous multiplication by a small set of two pairwise coefficients where the coefficients are the real and imaginary part of a limited number of points uniformly spread on the unit circle. Hence, each such multiplier forms half of a complex multiplier suitable for twiddle factor multiplication in FFT architectures. Based on trigonometric identities we propose a multiplier for a unit circle resolution of 32 points. Also, we revisit an earlier proposed multiplier for 16 points and show that the complexity can be reduced by using minimum adder constant multipliers compared with the earlier proposed CSD-based multipliers.
Place, publisher, year, edition, pages
Piscataway: IEEE , 2009. 1137-1140 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-51068DOI: 10.1109/ISCAS.2009.5117961ISI: 000275929800292ISBN: 978-1-4244-3827-3OAI: oai:DiVA.org:liu-51068DiVA: diva2:272635