Design of an FPGA Based JTAG Recorder for use in Production of IPTV Set-Top Boxes
Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesisAlternative title
Design av en FPGA-baserad JTAG-inspelare för användning i produktion av IPTV set-top boxar (Swedish)
This thesis evaluates the possibility to replace the manufacturer dependent JTAG device used in the production tests of IPTV set-top boxes for storing the boot loader in the main memory in order to start the box for the first time. An FPGA based prototype was built in order to see if it is possible to record the JTAG signals, to an external DDR SDRAM, without understanding them and be able to perform a delayed playback resulting in the same bahavoir as with the original JTAG device.Overall the thesis was succesful and it shows that it is infact feasible to create a JTAG recorder based on an FPGA. A lot of data is used for storing the sequence though so the use of a fast memory is cruicial. However in this thesis the speed of both the recording and the delayed playback was reduced in order to work properly.
Place, publisher, year, edition, pages
2009. , 41 p.
JTAG, FPGA, Set-Top Box, DDR SDRAM, UART
IdentifiersURN: urn:nbn:se:liu:diva-50504ISRN: LiTH-ISY-EX--09/4294--SEOAI: oai:DiVA.org:liu-50504DiVA: diva2:274070
2009-09-25, Algoritmen, Linköpings Universitet, Linköping, 10:15 (Swedish)