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Design of High‐Speed, Low‐Power, Nyquist Analog‐to‐Digital Converters
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2009 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

The scaling of CMOS technologies has increased the performance of general purposeprocessors and DSPs while analog circuits designed in the same process have not been ableto utilize the process scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. In order to design efficient analog‐to‐digital converters in nanoscale CMOS there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of what the process has tooffer.

This thesis explores the power dissipation of Nyquist rate analog‐to‐digital converters andtheir lower bounds, set by both the thermal noise limit and the minimum device and feature sizes offered by the process. The use of digital error correction, which allows for lowaccuracy analog components leads to a power dissipation reduction. Developing the bounds for power dissipation based on this concept, it is seen that the power of low‐to‐medium resolution converters is reduced when going to more modern CMOS processes, something which is supported by published results.

The design of comparators is studied in detail and a new topology is proposed which reduces the kickback by 6x compared to conventional topologies. This comparator is used in two flash ADCs, the first employing redundancy in the comparator array, allowing for the use of small sized, low‐power, low‐accuracy comparators to achieve an overall low‐power solution. The flash ADC achieves 4 effective bits at 2.5 GS/s while dissipating 30 mW of power.

The concept of low‐accuracy components is taken to its edge in the second ADC which oes not include a reference network, instead relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference‐free ADC achieves a resolution of 3.69 bits at 1.5 GS/s while dissipation 23 mW showing that process variations not necessarily must be seen as detrimental to circuit performance but rather can be seen as a source of diversity.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press , 2009. , 57 p.
Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1423
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-51375Local ID: LiU‐TEK‐LIC‐2009:31ISBN: 978‐91‐7393‐486‐2 OAI: oai:DiVA.org:liu-51375DiVA: diva2:274483
Presentation
2009-12-18, Glashuset, Campus Valla, Linköpings universitet, Linköping, 10:15 (Swedish)
Opponent
Supervisors
Available from: 2009-10-29 Created: 2009-10-29 Last updated: 2009-10-29Bibliographically approved
List of papers
1. Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters
Open this publication in new window or tab >>Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters
2009 (English)In: IEEE Transactions on Circuits and Systems I-Regular Papers, ISSN 1549-8328, Vol. 56, no 3, 509-518 p.Article in journal (Refereed) Published
Abstract [en]

A very important limitation of high-speed analog-todigital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and todays designs.

Keyword
Analog-digital conversion, CMOS analog integrated circuits, high-speed electronics, power demand
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-17615 (URN)10.1109/TCSI.2008.2002548 (DOI)
Available from: 2009-04-07 Created: 2009-04-06 Last updated: 2011-04-20Bibliographically approved
2. A kick-back reduced comparator for a 4-6-bit 3-GS/S flash ADC in a 90nm CMOS process
Open this publication in new window or tab >>A kick-back reduced comparator for a 4-6-bit 3-GS/S flash ADC in a 90nm CMOS process
2007 (English)In: Proceedings of the 14th International Conference, Mixed Design of Integrated Circuits and Systems, Lodz, Poland: Technical university of Lodz , 2007, , 195-198 p.195-195 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a kick-back reduced comparator based on a senseamplifier type comparator. The kick-back charge and resulting voltage peak is reduced by 6x, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%.

Place, publisher, year, edition, pages
Lodz, Poland: Technical university of Lodz, 2007. 195-198 p.
Keyword
comparator, kick-back, low-power, flash ADC, CMOS
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-38260 (URN)10.1109/MIXDES.2007.4286149 (DOI)43306 (Local ID)83-922632-9-4 (ISBN)43306 (Archive number)43306 (OAI)
Conference
14th International Conference Mixed Design of Integrated Circuits and Systems, 21-23 June, Ciechocinek, Poland
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-04-20Bibliographically approved
3. A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS
Open this publication in new window or tab >>A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS
2010 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, 215-222 p.Article in journal (Refereed) Published
Abstract [en]

A 2.5 GS/s flash ADC, fabricated in 90nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade‐offs. The redundancy removes the need to control comparator offsets, allowing the large process‐variation induced mismatch of small devices in nanometer technologies. This enables the use of small‐sized, ultra‐low‐power comparators with clock‐gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low‐power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-51374 (URN)10.1007/s10470-009-9391-x (DOI)000280593900002 ()
Note
The original publication is available at www.springerlink.com: Timmy Sundström and Atila Alvandpour, A 6‐bit 2.5‐GS/s Flash ADC using Comparator Redundancy for Low Power in 90nm CMOS, 2010, Analog Integrated Circuits and Signal Processing, (64), 3, 215-222. http://dx.doi.org/10.1007/s10470-009-9391-x Copyright: Springer Science Business Media http://www.springerlink.com/ Available from: 2009-10-29 Created: 2009-10-29 Last updated: 2017-12-12Bibliographically approved
4. Utilizing Process Variations for Reference Generation in a Flash ADC
Open this publication in new window or tab >>Utilizing Process Variations for Reference Generation in a Flash ADC
2009 (English)In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, ISSN 1549-7747, Vol. 56, no 5, 364-368 p.Article in journal (Refereed) Published
Abstract [en]

This brief presents an experimental study on how to take advantage of the increasing process variations in nanoscale CMOS technologies to achieve small and low-power high-speed analog-to-digital converters (ADCs). Particularly, the need for a reference voltage generation network has been eliminated in a 4-bit Flash ADC in 90-nm CMOS, with small-sized comparators. The native comparator offsets, resulting from the process-variation-induced mismatch, are used as the only source of reference levels, and redundancy is used to acquire the desired resolution. The measured performance of the 1.5-GS/s ADC is comparable to traditional state-of-the art ADCs and dissipates 23 mW.

Keyword
Flash analog-to-digital converter (ADC), high-performance design, parameter variation
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-19138 (URN)10.1109/TCSII.2009.2019165 (DOI)
Available from: 2009-06-12 Created: 2009-06-12 Last updated: 2011-04-20Bibliographically approved

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