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Optimized On-Chip Pipelining of Memory-Intensive Computations on the Cell BE
Linköping University, Department of Computer and Information Science, PELAB - Programming Environment Laboratory. Linköping University, The Institute of Technology.ORCID iD: 0000-0001-5241-0026
FernUniversität in Hagen, Germany.
2008 (English)In: ACM SIGARCH Computer Architecture News, ISSN 0163-5964, Vol. 36, no 5, 36-45 p.Article in journal (Refereed) Published
Abstract [en]

Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and thus increase performance, by expressing our application as a task graph, by running dependent tasks concurrently and by pipelining results directly from task to task where possible, instead of buffering in off-chip memory. To maximize bandwidth savings and balance load simultaneously, we solve a mapping problem of tasks to SPEs on the Cell BE. We present three approaches: an integer linear programming formulation that allows to compute Paretooptimal mappings for smaller task graphs, general heuristics, and a problem speci c approximation algorithm. We validate the mappings for dataparallel computations and sorting.

Place, publisher, year, edition, pages
ACM , 2008. Vol. 36, no 5, 36-45 p.
Keyword [en]
Heterogeneous multicore processor, Cell Broadband Engine, Pipelining, Parallel computing, Stream computing, Mapping, Integer Linear Programming, Program optimization
National Category
Computer Science
URN: urn:nbn:se:liu:diva-52029DOI: 10.1145/1556444.1556450OAI: diva2:278928
VR Integrated Software PipeliningSSF DSP Platform for Emerging Applications in Telecommunication and Multimedia
Journal version of our MCC-2008 workshop paper with the same title.Available from: 2009-11-30 Created: 2009-11-30 Last updated: 2014-10-08

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PELAB - Programming Environment LaboratoryThe Institute of Technology
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