Optimized On-Chip Pipelining of Memory-Intensive Computations on the Cell BE
2008 (English)In: ACM SIGARCH Computer Architecture News, ISSN 0163-5964, Vol. 36, no 5, 36-45 p.Article in journal (Refereed) Published
Multiprocessors-on-chip, such as the Cell BE processor, regularly suffer from restricted bandwidth to off-chip main memory. We propose to reduce memory bandwidth requirements, and thus increase performance, by expressing our application as a task graph, by running dependent tasks concurrently and by pipelining results directly from task to task where possible, instead of buffering in off-chip memory. To maximize bandwidth savings and balance load simultaneously, we solve a mapping problem of tasks to SPEs on the Cell BE. We present three approaches: an integer linear programming formulation that allows to compute Paretooptimal mappings for smaller task graphs, general heuristics, and a problem speci c approximation algorithm. We validate the mappings for dataparallel computations and sorting.
Place, publisher, year, edition, pages
ACM , 2008. Vol. 36, no 5, 36-45 p.
Heterogeneous multicore processor, Cell Broadband Engine, Pipelining, Parallel computing, Stream computing, Mapping, Integer Linear Programming, Program optimization
IdentifiersURN: urn:nbn:se:liu:diva-52029DOI: 10.1145/1556444.1556450OAI: oai:DiVA.org:liu-52029DiVA: diva2:278928
ProjectsVR Integrated Software PipeliningSSF DSP Platform for Emerging Applications in Telecommunication and Multimedia
Journal version of our MCC-2008 workshop paper with the same title.2009-11-302009-11-302014-10-08