Analysis and optimization of fault-tolerant embedded systems with hardened processors
2009 (English)In: Proceedings -Design, Automation and Test in Europe, DATE, 2009, 682-687 p.Conference paper (Refereed)
In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process re-execution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of re-executions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.
Place, publisher, year, edition, pages
2009. 682-687 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-52965DOI: 10.1109/DATE.2009.5090752ISI: 000273246700123ISBN: 978-1-4244-3781-8OAI: oai:DiVA.org:liu-52965DiVA: diva2:286415
2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09; Nice; France