Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures
2010 (English)In: CIRCUITS SYSTEMS AND SIGNAL PROCESSING, ISSN 0278-081X, Vol. 29, no 1, 81-101 p.Article in journal (Refereed) Published
Analog-to-digital converters based on sigma-delta modulation have shown promising performance, with steadily increasing bandwidth. However, associated with the increasing bandwidth is an increasing modulator sampling rate, which becomes costly to decimate in the digital domain. Several architectures exist for the digital decimation filter, and among the more common and efficient are polyphase decomposed finite-length impulse response (FIR) filter structures. In this paper, we consider such filters implemented with partial product generation for the multiplications, and carry-save adders to merge the partial products. The focus is on the efficient pipelined reduction of the partial products, which is done using a bit-level optimization algorithm for the tree design. However, the method is not limited only to filter design, but may also be used in other applications where high-speed reduction of partial products is required. The presentation of the reduction method is carried out through a comparison between the main architectural choices for FIR filters: the direct-form and transposed direct-form structures. For the direct-form structure, usage of symmetry adders for linear-phase filters is investigated, and a new scheme utilizing partial symmetry adders is introduced. The optimization results are complemented with energy dissipation and cell area estimations for a 90 nm CMOS process.
Place, publisher, year, edition, pages
2010. Vol. 29, no 1, 81-101 p.
FIR, Polyphase, Sigma-delta, CIC, Optimization, Integer linear programming, Decimation, Digital filter, Carry-save
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-53826DOI: 10.1007/s00034-009-9116-5ISI: 000273808300006OAI: oai:DiVA.org:liu-53826DiVA: diva2:292214
The original publication is available at www.springerlink.com:
Anton Blad and Oscar Gustafsson, Integer Linear Programming-Based Bit-Level Optimization for High-Speed FIR Decimation Filter Architectures, 2010, CIRCUITS SYSTEMS AND SIGNAL PROCESSING, (29), 1, 81-101.
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