High-performance and low-power challenges for sub-70nm microprocessor circuits
2002 (English)In: Proceedings of the IEEE Custom Integrated Circuits Conference, 2002, 125-128 p.Conference paper (Refereed)
CMOS technology scaling is becoming difficult beyond 70nm node, raising new design challenges for highperformance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, and (iii) worsening global on-chip interconnect scaling trend, are described.
Place, publisher, year, edition, pages
2002. 125-128 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-54008OAI: oai:DiVA.org:liu-54008DiVA: diva2:296808
IEEE Custom Integrated Circuits Conference