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High-performance, low-power, and leakage-tolerance challenges for sub-70nm microprocessor circuits
Intel Corporation, Hillsboro, USA.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Intel Corporation, Hillsboro, USA.
Intel Corporation, Hillsboro, USA.
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2002 (English)In: Proceedings fo the 28th European Solid-Stated Circuits Conference, 2002, 315-321 p.Conference paper (Refereed)
Abstract [en]

CMOS technology scaling is becoming difficult beyond 70nm node, raising new design challenges for high-performance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, (iii) worsening global on-chip interconnect scaling trend, and (iv) high-performance robust datapath circuits enabling up to 10GHz ALU and instruction scheduler loops in 130nm dual-Vt CMOS technology are described.

Place, publisher, year, edition, pages
2002. 315-321 p.
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-54010OAI: diva2:296985
IEEE Solid-State Circuits Conference
Available from: 2010-02-18 Created: 2010-02-18 Last updated: 2010-03-23

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Alvandpour, Atila
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