High-performance, low-power, and leakage-tolerance challenges for sub-70nm microprocessor circuits
2002 (English)In: Proceedings fo the 28th European Solid-Stated Circuits Conference, 2002, 315-321 p.Conference paper (Refereed)
CMOS technology scaling is becoming difficult beyond 70nm node, raising new design challenges for high-performance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, (iii) worsening global on-chip interconnect scaling trend, and (iv) high-performance robust datapath circuits enabling up to 10GHz ALU and instruction scheduler loops in 130nm dual-Vt CMOS technology are described.
Place, publisher, year, edition, pages
2002. 315-321 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-54010OAI: oai:DiVA.org:liu-54010DiVA: diva2:296985
IEEE Solid-State Circuits Conference