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A sub-130-nm conditional keeper technique
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
Microprocessor Res. Labs., Intel Corp., Hillsboro, OR .
2002 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 37, no 5, 633-638 p.Article in journal (Refereed) Published
Abstract [en]

Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction

Place, publisher, year, edition, pages
2002. Vol. 37, no 5, 633-638 p.
Keyword [en]
Burn-in, conditional, dynamic circuits, keeper, leakage, robustness.
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-54012DOI: 10.1109/4.997857OAI: diva2:296994
Available from: 2010-02-18 Created: 2010-02-18 Last updated: 2010-03-23

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Alvandpour, Atila
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ReferencesLink to record
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