A 130-nm 6-GHz 256x32 bit leakage-tolerant register file
2002 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 37, no 5, 624-632 p.Article in journal (Refereed) Published
Describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-Vt usage, and 50% keeper downsizing. Gate-source underdrive of -V cc on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-Vt bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703× bitline active leakage reduction, enabling continued Vt scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented
Place, publisher, year, edition, pages
2002. Vol. 37, no 5, 624-632 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-54013DOI: 10.1109/4.997856OAI: oai:DiVA.org:liu-54013DiVA: diva2:296996