Separation and Extraction of Short-Circuit Power Consumption in Digital CMOS VLSI Circuits
1998 (English)In: ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design, 1998, 245-249 p.Conference paper (Refereed)
In this paper, we present a new technique which indirectly separates and extracts the total short-circuit power consumption of digital CMOS circuits. We avoid a direct encounter with the complex behavior of the short-circuit currents. Instead, we separate the dynamic power consumption from the total power and extract the total short-circuit power. The technique is based on two facts: first, the short-circuit power consumption disappears at a Vdd close to VT and, secondly, the total capacitance depends on supply voltage in a sufficiently weak way in standard CMOS circuits. Hence, the total effective capacitance can be estimated at a low Vdd. To avoid reducing Vdd below the specified forbidden level, a polynomial is used to estimate the power versus supply voltage down to VT based on a small voltage sweep over the allowed supply voltage levels. The result shows good accuracy for the short-circuit current ranges of interest.
Place, publisher, year, edition, pages
1998. 245-249 p.
Short-circuit current, Power consumption, Power estimation.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-54104DOI: 10.1145/280756.280919OAI: oai:DiVA.org:liu-54104DiVA: diva2:299560
International Symposium on Low-Power Electronics and Design, 10-12 August 1998, Monterey, California, USA