Low Power and Low Voltage CMOS Digital Circuit Techniques
1998 (English)In: In proceedings of: International Symposium on Low Power Electronics and Design. Invited paper., 1998, 7-10 p.Conference paper (Other academic)
One of many important factors affecting power consumption is the choice of circuit technique for logic, latches and flip-flops. We analyze the power consumption at circuit level and use the results to guide the choice of circuit technique. Several types of latches and flip-flops are compared regarding power consumption and speed. Comparing logic clearly indicates that simple static logic in general have the lowest power consumption. Another very important factor affecting power consumption is the supply voltage. We discuss the effect of low supply voltage on the choice of circuit technique.
Place, publisher, year, edition, pages
1998. 7-10 p.
Low Power, Low voltage, CMOS, Digital circuits.
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-54111DOI: http://doi.acm.org/10.1145/280756.280759OAI: oai:DiVA.org:liu-54111DiVA: diva2:299613