2-D Realization of WiMAX Channel Interleaver for Efficient Hardware Implementation
2009 (English)In: Proceedings of World Academy of Science, Engineering and Technology (ISSN: 2070-3740), 2009, 25-29 p.Conference paper (Refereed)
The direct implementation of interleaver functions in WiMAX is not hardware efficient due to presence of complex functions. Also the conventional method i.e. using memories for storing the permutation tables is silicon consuming. This work presents a 2-D transformation for WiMAX channel interleaver functions which reduces the overall hardware complexity to compute the interleaver addresses on the fly. A fully re-configurable architecture for address generation in WiMAX channel interleaver is presented, which consume 1.1 k-gates in total. It can be configured for any block size and any modulation scheme in WiMAX. The presented architecture can run at a frequency of 200 MHz, thus fully supporting high bandwidth requirements for WiMAX.
Place, publisher, year, edition, pages
2009. 25-29 p.
, World Academy of Science, Engineering and Technology, ISSN 2070-3740
Interleaver, deinterleaver, WiMAX, 802.16e
Engineering and Technology Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-55303OAI: oai:DiVA.org:liu-55303DiVA: diva2:315971
International Conference on Wireless Communication and Sensor Networks