Towards Radix-4, Parallel Interleaver Design to Support High-Throughput Turbo Decoding for Re-Configurability
2010 (English)Conference paper (Refereed)
Parallel, radix-4 turbo decoding is used to enhance the throughput and at the same time reduce the overall memory cost. The bottleneck is the higher complexity associated with radix-4 parallel interleaver implementation. This paper addresses the implementation issues of radix-4, parallel interleaver and also proposes necessary modifications in the interleaver algorithms for parallel address generation. It presents a re-configurable architecture which enables the use of same turbo decoding core to be used for multiple standards. The proposed interleaver architecture is capable of handling the memory conflicts on-the-fly. It consumes 12.5K gates and can run at a frequency of 285MHz, thus supporting a throughput of 173.3Mpbs, which can cover most of the emerging communication standards.
Place, publisher, year, edition, pages
IEEE , 2010. 1-5 p.
Radix-4 interleaver, Parallel turbo decoding, HSPA, DVB, WiMAX, LTE
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-55305DOI: 10.1109/SARNOF.2010.5469723ISBN: 978-1-4244-5592-8OAI: oai:DiVA.org:liu-55305DiVA: diva2:315974
33rd IEEE SARNOFF Symposium, Princeton, NJ, USA