Implementation of a high-speed parallel Turbo decoder for 3GPP LTE terminals
2009 (English)Conference paper (Refereed)
This paper presents a parameterized parallel Turbo decoder for 3GPP LTE terminals. To support the high peak data-rate defined in the forthcoming 3GPP LTE standard, turbo decoder with a throughout beyond 150 Mbit/s is needed as a key component of the radio baseband chip. By exploiting the tradeoff of precision, speed and area consumption, a turbo decoder with eight parallel SISO units is implemented to meet the throughput requirement. The turbo decoder is synthesized, placed and routed using 65 nm CMOS technology. It achieves a throughput of 152 Mbit/s and occupies an area of 0.7 mm2 with estimated power consumption being 650 mW.
Place, publisher, year, edition, pages
IEEE , 2009. 481-484 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-56217DOI: 10.1109/ASICON.2009.5351623ISI: 000275924100117ISBN: 978-1-4244-3868-6OAI: oai:DiVA.org:liu-56217DiVA: diva2:317037
IEEE 8th International Conference on ASIC, ASICON'09.