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Investigation of Processor Implementations inNoGap
Linköping University, Department of Electrical Engineering.
2010 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

ASIP (Application Specific Instruction set Processors) are starting to replacemonolithic ASIC and general purpose processors in a wide variety of fields due tothe features of ASIP, such as more flexibility and higher efficiency. NoGap (NovelGenerator of Accelerator and Processor framework) is an innovative tool forASIP design, which provides designers with the advantages such as automationand design freedom which are derived from both ADL (Architecture DescriptionLanguage) and HDL (Hardware Description Language).

The thesis presents two case studies, where we used NoGap to design RISCprocessors, with DSP extensions. The NoGap generated SystemVerilog code wassynthesized in a Virtex-4 LX80 FPGA with speedgrade 12 and ASIC flow in 65 nmCMOS technology with low power standard normal threshold voltage library. PIONEERwhich is a simple processor was successfully tested in an FPGA by runningsome typical DSP application such as FIR filters and DCT. PIONEER met timingclosure at 203 MHz and 300 MHz in FPGA and ASIC flow individually. SENIORprocessor which has been designed, optimized and taped-out by division of ComputerEngineering at the University of Linköping for nearly 5 years were developedagain but using NoGap for less than 3 man-weeks. NoGap SENIOR met timingclosure at 85 MHz which is close to original SENIOR in of FPGA synthesis reports.The resulting of maximum frequency of the ASIC design were 215 MHz,which is only 10% less than original SENIOR in 65nm technology with 100% lowpower logic cell. Examining the critical paths we could conclude that hardwaresynthesize by NoGap was not a limiting factor. In the conclusion of the thesis, weoffer some suggestions to improve limitation for NoGap or other similar tools.

Place, publisher, year, edition, pages
2010. , 74 p.
Keyword [en]
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-56988ISRN: LiTH-ISY-EX- -10/4340- -SEOAI: diva2:323102
2010-06-03, Systemet, 13:15 (English)
Available from: 2010-06-10 Created: 2010-06-09 Last updated: 2011-05-18Bibliographically approved

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Wang, Ching-han
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Department of Electrical Engineering
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