Evaluation of partial reconfiguration for FPGA debugging
Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Reconfigurable computing is an old concept that during the past couple of decades has become increasingly popular. The concept combines the flexibility of software with the performance of hardware. One important contributing factor to the uprising in popularity is the presence of FPGAs (field-programmable gate arrays), which realize the concept by allowing the hardware to be reconfigured dynamically. The current state of reconfigurable computing is discussed further in the thesis.
Debugging is a vital part in the development of a hardware design. It can be done in several ways depending on the situation. The most common way is to perform simulations but in some cases the fault-finding has to be done when the design is implemented in hardware.
In this thesis a framework concept is designed that utilizes and evaluates some of the reconfigurable computing ideas. The framework provides debugging possibilities for FPGA designs in a novel way, with a modular system where each module provide means to aid finding a specific fault. The framework is added to an existing design, and offers the user a glimpse into the design behavior and the hardware it runs on.
One of the debug modules will be released separately under a free license. It allows the developer to see the contents of the memories in a design without requiring special debugging equipment.
Place, publisher, year, edition, pages
2010. , 71 p.
fpga, partial reconfiguration, dynamic reconfigurability, reconfigurable computing, debugging
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-57714ISRN: LiTH-ISY-EX--10/4390--SEOAI: oai:DiVA.org:liu-57714DiVA: diva2:327626
2010-06-18, Glashuset, B-huset, Linköpings Universitet, Linköping, 13:15 (English)