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Capacitance analysis for a metal-insulator-semiconductor structure with an ultra-thin oxide layer
Chalmers University of Technology.
Chalmers University of Technology.ORCID iD: 0000-0001-6235-7038
2003 (English)In: Applied Physics A: Materials Science & Processing, ISSN 0947-8396, E-ISSN 1432-0630, Vol. 76, no 1, 27-31 p.Article in journal (Refereed) Published
Abstract [en]

We have studied theoretically the capacitance characteristics of a metal-insulator-semiconductor structure with an ultra-thin oxide layer by self-consistently solving Schrodinger and Poisson equations. It is demonstrated that a diffused interface between Si and SiO2 results in a better agreement between the theoretical prediction of conduction current and experimental I-V data. The calculated steady-state capacitance, obtained both analytically and numerically, increases following the increase of the gate bias when the gate bias is small; it reaches a saturation value at intermediate gate bias. The capacitance decreases with increasing gate bias when the gate bias is rather large due to the depletion of the gate material. Simple analytical expressions for the gate capacitance are derived, based on quantum-mechanical considerations, for future device design. The steady-state capacitance of a metal-insulator-semiconductor structure with an oxide layer of 1.5-2.0 nm by state-of-the-art technology is 20 mF/m(2), while it is 40 mF/m(2) when the practical limit of SiO2 layer thickness, i.e. 10-12 Angstrom, is reached.

Place, publisher, year, edition, pages
Springer Science Business Media , 2003. Vol. 76, no 1, 27-31 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-59180DOI: 10.1007/s00339-002-1472-yISI: 000180701200005OAI: oai:DiVA.org:liu-59180DiVA: diva2:350157
Available from: 2010-09-10 Created: 2010-09-09 Last updated: 2017-12-12

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Willander, Magnus

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