liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Implementation of Low Power, Wide Range ADPLL for Video Applications
Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, Department of Electrical Engineering, Electronics System.
2010 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesisAlternative title
Konstruktion av en bredbandig, heldigital, lågeffekts-PLL för videotillämpningar (Swedish)
Abstract [en]

Phase locked loop (PLLs) are the keystone for the electronic as well as for the communication circuits. Without any exaggeration, PLLs are found almost in every electronic and communication devices. Countless research has been performed, for the modification and enhancement of the PLLs circuit. While, due to the numerous advantage of the digital circuitry, the recent research is focusing on the all digital implementation of the PLLs. Therefore, it was competitive to touch with burning research.

Low power and wide range all digital phase locked loop (ADPLL), for video applications is presented. ADPLL has an operating input frequency between 10kHz to 150 kHz and output frequency between 10 MHz to 300 MHz. The phase frequency detector (PFD) is based on D-flip flops, having two output error and direction signal. The traditional charge pump (CP) is replaced by time-to-digital converters (TDC) and analog low pass filter (LPF) by digital low pass filter (digital-LPF). For completely digital architecture, voltage controlled oscillator (VCO) is replaced by the digitally controlled oscillator (DCO). In DCO, eleven bits are dedicated for controlling bits, two bits for biasing and one bit for enable the DCO. The designed steps for ADPLL were almost similar to the designed steps of a second order analog PLL. The ADPLL is implemented on a CMOS 65-nm technology.

Place, publisher, year, edition, pages
2010. , 95 p.
Keyword [en]
PLL, Digital, Low Power, Wide Range
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-59307ISRN: LiTH-ISY-EX--10/4407--SEOAI: oai:DiVA.org:liu-59307DiVA: diva2:351139
Presentation
2010-08-12, Nollstället, 13:00 (English)
Uppsok
Technology
Supervisors
Examiners
Available from: 2010-09-13 Created: 2010-09-13 Last updated: 2010-09-13Bibliographically approved

Open Access in DiVA

fulltext(1167 kB)1122 downloads
File information
File name FULLTEXT01.pdfFile size 1167 kBChecksum SHA-512
57d569d961a9fe0a2dba784499a23447cddc83e7a1ba2c625fc2e4a219fa51f23d1736f296f8c101417c6fd819617cddf279762993adfca5d8d77659abdc10b9
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
Qureshi, Abdul RaheemQazi, Haris
By organisation
Electronics System
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 1122 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 580 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf