Multi-temperature testing for core-based system-on-chip
2010 (English)In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2010, 208-213 p.Conference paper (Refereed)
Recent research has shown that different defects can manifest themselves as failures at different temperature spectra. Therefore, we need multi-temperature testing which applies tests at different temperature levels. In this paper, we discuss the need and problems for testing core-based systems-on-chip at different temperatures. To address the long test time problem for multitemperature test, we propose a test scheduling technique that generates the shortest test schedules while keeping the cores under test within a temperature interval. Experimental results show the efficiency of the proposed technique.
Place, publisher, year, edition, pages
IEEE , 2010. 208-213 p.
Multi-temperature testing; System-on-chip test; Test scheduling; Thermal-aware test
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-59108DOI: 10.1109/DATE.2010.5457209ISBN: 978-1-4244-7054-9OAI: oai:DiVA.org:liu-59108DiVA: diva2:352341
Design, Automation and Test in Europe Conference and Exhibition, DATE 2010; Dresden; Germany