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A Single-channel, 2.4 GS/s, 4.9 ENOB at Nyquist, Pipeline ADC in 65nm CMOS
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2010 (English)In: Swedish System on Chip Conference, SSoCC, Kolmården, 2010Conference paper, Published paper (Other academic)
Abstract [en]

This paper presents a high-speed single channel pipeline analog-to-digital converter sampling at 2.4 GS/s which, to the authors’ best knowledge, is the fastest reported for pipeline converters. The use of a time-borrowing clocking scheme eliminates the comparator latency from the critical path and together with the use of fast open-loop current-mode amplifiers the high sample rate is achieved. Implemented in a 65nm general purpose CMOS technology the effective number of bits is above 4.7 in the Nyquist band, being 5.4 and 4.9 at DC and Nyquist respectively. This shows that very fast pipeline ADCs are possible to implement as key building blocks in interleaved structures.

Place, publisher, year, edition, pages
2010.
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Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-59561OAI: oai:DiVA.org:liu-59561DiVA: diva2:352501
Available from: 2010-09-21 Created: 2010-09-21 Last updated: 2010-10-01

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Sundström, TimmySvensson, ChristerAlvandpour, Atila

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