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Power Efficient Redundant Execution for Chip Multiprocessors
Indian Institute of Science, Bangalore.
Indian Institute of Science, Bangalore.
University of Wisconsin-Madison.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
2009 (English)In: Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June 29, 2009., 2009, 1-6 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.

Place, publisher, year, edition, pages
2009. 1-6 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-59588OAI: oai:DiVA.org:liu-59588DiVA: diva2:352609
Available from: 2010-09-21 Created: 2010-09-21 Last updated: 2010-09-30

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Larsson, Erik

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf