liu.seSearch for publications in DiVA
Change search
ReferencesLink to record
Permanent link

Direct link
Power Efficient Redundant Execution for Chip Multiprocessors
Indian Institute of Science, Bangalore.
Indian Institute of Science, Bangalore.
University of Wisconsin-Madison.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
2009 (English)In: Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June 29, 2009., 2009, 1-6 p.Conference paper (Refereed)
Abstract [en]

This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.

Place, publisher, year, edition, pages
2009. 1-6 p.
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-59588OAI: diva2:352609
Available from: 2010-09-21 Created: 2010-09-21 Last updated: 2010-09-30

Open Access in DiVA

fulltext(264 kB)466 downloads
File information
File name FULLTEXT01.pdfFile size 264 kBChecksum SHA-512
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
Larsson, Erik
By organisation
ESLAB - Embedded Systems LaboratoryThe Institute of Technology
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar
Total: 466 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Total: 162 hits
ReferencesLink to record
Permanent link

Direct link