Power Efficient Redundant Execution for Chip Multiprocessors
2009 (English)In: Workshop on Dependable and Secure Nanocomputing, Lisbon, Portugal, June 29, 2009., 2009, 1-6 p.Conference paper (Refereed)
This paper describes the design of a power efficient microarchitecture for transient fault detection in chip multiprocessors (CMPs) We introduce a new per-core dynamic voltage and frequency scaling (DVFS) algorithm for our architecture that significantly reduces power dissipation for redundant execution with a minimal performance overhead. Using cycle accurate simulation combined with a simple first order power model, we estimate that our architecture reduces dynamic power dissipation in the redundant core by an mean value of 79% and a maximum of 85% with an associated mean performance overhead of only 1.2%.
Place, publisher, year, edition, pages
2009. 1-6 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-59588OAI: oai:DiVA.org:liu-59588DiVA: diva2:352609