liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
On Minimization of Peak Power for Scan Circuit during Test
Indian Institute of Science.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Indian Institute of Science.
Auburn University.
2009 (English)In: Proceedings of the 14th IEEE European Test Symposium, ETS 2009, 2009, 25-30 p.Conference paper, Published paper (Refereed)
Abstract [en]

Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.

Place, publisher, year, edition, pages
2009. 25-30 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-59591DOI: 10.1109/ETS.2009.36ISBN: 978-0-7695-3703-0 (print)OAI: oai:DiVA.org:liu-59591DiVA: diva2:352613
Conference
14th IEEE European Test Symposium, ETS 2009; Sevilla; Spain
Note

©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Jaynarayan T. Tudu, Erik Larsson, Virendra Singh and Vishwani Agrawal, On Minimization of Peak Power for Scan Circuit during Test, 2009, European Test Symposium (ETS 2009), Sevilla, Spain, May 25-29, 2009, 25-30.

Available from: 2010-09-29 Created: 2010-09-21 Last updated: 2014-09-05Bibliographically approved

Open Access in DiVA

fulltext(243 kB)112 downloads
File information
File name FULLTEXT02.pdfFile size 243 kBChecksum SHA-512
0383b068c7ada1dc1bf4bf88dfd7399ffc463c0a2652c41796cb6f3c835ce0eef3846e5d7e8c6b9829751787513085fdb114988cdaf015ea206da058710163a0
Type fulltextMimetype application/pdf

Other links

Publisher's full text

Authority records BETA

Larsson, Erik

Search in DiVA

By author/editor
Larsson, Erik
By organisation
ESLAB - Embedded Systems LaboratoryThe Institute of Technology
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar
Total: 112 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 54 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf