Ultra low-power devices are being developed for
embedded applications in bio-medical electronics, wireless
sensor networks, environment monitoring and protection,
etc. The testing of these low-cost, low-power devices is a
daunting task. Depending on the target application, there
are stringent guidelines on the number of defective parts
per million shipped devices. At the same time, since such
devices are cost-sensitive, test cost is a major consideration.
Since system-level power-management techniques are
employed in these devices, test generation must be powermanagement-
aware to avoid stressing the power
distribution infrastructure in the test mode. Structural test
techniques such as scan test, with or without compression,
can result in excessive heat dissipation during testing and
damage the package. False failures may result due to the
electrical and thermal stressing of the device in the test
mode of operation, leading to yield loss. This paper
considers different aspects of testing low-power devices
and some new techniques to address these problems.
Springer , 2009, 1.