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Power-Aware System-Level DfT and Test Planning
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
2009 (English)In: Power-Aware Testing and Test Strategies for Low Power Devices / [ed] Girard, Patrick; Nicolici, Nicola; Wen, Xiaoqing, Springer , 2009, 1Chapter in book (Other academic)
Abstract [en]

Ultra low-power devices are being developed for

embedded applications in bio-medical electronics, wireless

sensor networks, environment monitoring and protection,

etc. The testing of these low-cost, low-power devices is a

daunting task. Depending on the target application, there

are stringent guidelines on the number of defective parts

per million shipped devices. At the same time, since such

devices are cost-sensitive, test cost is a major consideration.

Since system-level power-management techniques are

employed in these devices, test generation must be powermanagement-

aware to avoid stressing the power

distribution infrastructure in the test mode. Structural test

techniques such as scan test, with or without compression,

can result in excessive heat dissipation during testing and

damage the package. False failures may result due to the

electrical and thermal stressing of the device in the test

mode of operation, leading to yield loss. This paper

considers different aspects of testing low-power devices

and some new techniques to address these problems.

Place, publisher, year, edition, pages
Springer , 2009, 1.
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-59592ISBN: 978-1-4419-0927-5OAI: diva2:352614
Available from: 2010-09-21 Created: 2010-09-21 Last updated: 2013-05-13Bibliographically approved

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