Test Time Analysis for IEEE P1687
2010 (English)In: Proceedings of the Asian Test Symposium, 2010, 455-460 p.Conference paper (Refereed)
The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test. A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test time in a P1687 context. The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.
Place, publisher, year, edition, pages
2010. 455-460 p.
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-59597DOI: 10.1109/ATS.2010.83ISBN: 978-076954248-5OAI: oai:DiVA.org:liu-59597DiVA: diva2:352621
2010 19th IEEE Asian Test Symposium, ATS 2010; Shanghai; China