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Scheduling Tests for Stacked 3D Chips under Power Constraints
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
2010 (English)In: Swedish SoC Conference 2010, Kolmården, Sweden, May 3-4, 2010 (not reviewed, not printed), 2010Conference paper, Published paper (Other academic)
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2010.
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Engineering and Technology
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URN: urn:nbn:se:liu:diva-59602OAI: oai:DiVA.org:liu-59602DiVA: diva2:352625
Available from: 2010-09-21 Created: 2010-09-21 Last updated: 2010-09-28

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SenGupta, BreetaIngelsson, UrbanLarsson, Erik

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ESLAB - Embedded Systems LaboratoryThe Institute of Technology
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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
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  • Other style
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  • de-DE
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