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Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
Indian Institute of Science.
Indian Institute of Science.
University of Wisconsin-Madison.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
2010 (English)In: The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10), Fairmont Chicago, Millennium Park, Chicago, Illinois, USA, June 28-July 1, 2010., 2010, 121-130 p.Conference paper, Published paper (Refereed)
Abstract [en]

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper we introduce a new energy-efficient fault-tolerant CMP architecture known as Redundant Execution using Critical Value Forwarding (RECVF). RECVF is based on two observations: (i) forwarding critical instruction results from the leading to the trailing core enables the latter to execute faster, and (ii) this speedup can be exploited to reduce energy consumption by operating the trailing core at a lower voltage-frequency level. Our evaluation shows that RECVF consumes 37% less energy than conventional dual modular redundant (DMR) execution of a program. It consumes only 1.26 times the energy of a nonfault- tolerant baseline and has a performance overhead of just 1.2%.

Place, publisher, year, edition, pages
2010. 121-130 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-59605DOI: 10.1109/DSN.2010.5544918ISBN: 978-1-4244-7499-8 (print)ISBN: 978-1-4244-7500-1 (print)OAI: oai:DiVA.org:liu-59605DiVA: diva2:352629
Conference
2010 IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2010; Chicago, IL; United States
Note

©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Pramod Subramanyan, Virendra Singh, Kewal K. Saluja and Erik Larsson, Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding, 2010, The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10), Fairmont Chicago, Millennium Park, Chicago, Illinois, USA, June 28-July 1, 2010, 121-130.

Available from: 2010-09-29 Created: 2010-09-21 Last updated: 2014-09-26Bibliographically approved

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Larsson, Erik

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CiteExportLink to record
Permanent link

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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
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  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
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