Energy-Efficient Redundant Execution for Chip Multiprocessors
2010 (English)In: Great Lakes Symposium on VLSI on (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010., New York, USA: ACM , 2010, 143-146 p.Conference paper (Refereed)
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.
Place, publisher, year, edition, pages
New York, USA: ACM , 2010. 143-146 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-59606DOI: 10.1145/1785481.1785516ISBN: 978-1-4503-0012-4OAI: oai:DiVA.org:liu-59606DiVA: diva2:352630
20th Great Lakes Symposium on VLSI, GLSVLSI 2010; Providence, RI; United States