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Scan Cells Reordering to Minimize Peak Power During Test Cycle: A Graph Theoretic Approach
Indian Institute of Science, Bangalore, India.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Indian Institute of Science, Bangalore, India.
Nara Institute of Science and Technology, Japan.
2010 (English)In: IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010., IEEE , 2010, 259-259 p.Conference paper (Refereed)
Abstract [en]

Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

Place, publisher, year, edition, pages
IEEE , 2010. 259-259 p.
, European Test Symposium, ISSN 1530-1877
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-59608DOI: 10.1109/ETSYM.2010.5512732ISBN: 978-1-4244-5833-2ISBN: 978-1-4244-5834-9OAI: diva2:352632
Available from: 2010-09-21 Created: 2010-09-21 Last updated: 2013-09-17

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Larsson, Erik
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ESLAB - Embedded Systems LaboratoryThe Institute of Technology
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ReferencesLink to record
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